The present invention relates to a control method for an operation system of a multiprocessor having buffer storage units.
Recent large computers of high performance often use a tightly coupled multiprocessor system in which instruction processors share a main storage unit. There are known two task scheduling methods of allocating a plurality of tasks to instruction processors in such a multiprocessor system. One is a load sharing method wherein tasks are allocated to instruction processors in accordance with the load of each instruction processor. The other is a shared-by-features method wherein a specific task is executed concentrically by one or a plurality of dedicated instruction processors. The load sharing method allows each instruction processor to be executable until its busy rate reaches 100%, so that it is generally used for a tightly coupled multiprocessor.
The load sharing method for a tightly coupled multiprocessor system is realized by a task dispatching algorithm. Namely, tasks each constituting a software execution unit are sequentially stored in an execution wait queue. An idle instruction processor searches the wait queue and selects an executable task if any to execute it (such selection and execution is called "dispatch"). Consider now an execution stop by the task dispatching algorithm wherein a certain task running on an instruction processor is stopped by an external factor such as an interruption or an internal factor caused by task execution such as a call for an OS function. When OS designates a new task after executing necessary processes, this new task has been designated heretofore irrespective of the previous task the instruction processor executed. Furthermore, the time period from when a task was executed to when it is stopped, is not constant but depends on both the characteristics of the task and the system state.
Another related background art of the present invention is a technique regarding a buffer storage unit. As the amount of tasks to be executed by recent computers becomes large, the necessary capacity of a main storage unit becomes considerably large. There is a bargain between the capacity and the speed and power consumption of semiconductor memory devices of a main storage unit. Using a number of memory devices compatible with high speed instruction processors is not effective in cost, space, and power consumption. This problem is generally solved by providing each instruction processor with a buffer storage unit of low capacity and high speed, and by bypassing an access to a main storage unit of large capacity and low speed. Such a buffer storage unit uses memory devices smaller in capacity and higher in speed than those of the main storage unit, so the whole capacity of the buffer storage unit is relatively small. Use of such a buffer storage unit relies upon the characteristics that a program uses data which is present concentrically, as viewed in a short time span, within a specific memory space. Data read in the buffer storage unit is reused or replaced with new data. Specifically, data used at a certain time period is read in the buffer storage unit and the data not used is pushed out from the buffer storage unit. In some cases, data is written back to the main storage unit so that the whole necessary memory space can be assigned to the small buffer storage unit. There is also known a configuration of a high speed multiprocessor system wherein there is provided an intermediate buffer storage unit for reducing a large difference of process speed between each instruction processor and a main storage unit. Such a configuration is disclosed, for example, in U.S. Pat. No. 4,442,487, U.S. Pat. No. 4,445,194, and Japanese Patent Laid-open Publication JP-A-64-51543.
A multiprocessor system having such buffer storage units can operate at a high speed if data to be used, referred, or changed by an instruction processor is present within the buffer storage unit (such a case is called hereinafter "iNBS"). However, if data is not present in the buffer storage unit (such a case is called hereinafter "NiBS"), it is necessary to access a low speed main storage unit to refer to or change necessary data. In the latter case, the time period necessary for data processing becomes several to several tens times as longer as the former case. It is therefore important to increase the percentage of iNBS in order to improve the system performance. This technique has been studied in various ways as the main issue of a cache technique. For example, Japanese Patent Laid-open Publication JP-A-1-133162 discloses the technique for controlling not to store specific data in a buffer storage unit. Japanese Patent Laid-open Publication JP-A-1-205250 discloses the hierarchic structure technique for a buffer storage unit.
Another related background art of the present invention is a coherence control technique for buffer storage units of a tightly coupled multiprocessor. The contents of a buffer storage unit are a copy of part of the main storage unit. If a plurality of instruction processors operate to change data in the main storage unit at the same memory space, it is necessary to change data in the main storage unit without any contradiction and also to change data in the other buffer storage units. As a technique relevant to this, there is disclosed in U.S. Pat. No. 4,136,386 a method of configuring a system which controls a memory access from the above-described viewpoint. Specifically, according to this method, there are disclosed various techniques for transferring data to be changed and stored in the main storage unit, between other buffer storage units. U.S. Pat. No. 4,775,955 discloses a coherence control method for data in buffer storage units which method uses software.
In a tightly coupled multiprocessor system using a load sharing control method described above, when a task running on an instruction processor is stopped by an external factor or an internal factor caused by task execution such as a call for an OS function, the data in the main storage unit used by the task is being stored at the instruction processor or the system buffer storage unit. If the task becomes again executable, an instruction processor to execute the task has been selected heretofore regardless of the instruction processor which previously executed the task. If the newly selected instruction processor differs from the instruction processor which previously executed the task (hereinafter called "previous instruction processor"), the data stored at the previous instruction processor becomes wasteful. Furthermore, if a different instruction processor executes the task, it becomes necessary to perform the above-described coherence control in order to make the contents of the main storage unit and buffer storage unit to be coincident with each other, on condition that data was written in the main storage unit. Therefore, the execution performance of the previous instruction processor lowers.